An architecture for high instruction level parallelism

High instruction level parallelism (ILP) can only be achieved when data $0~ and control flow constraints have been removed or reduced. Data jlow constraints, not inherent in the original code, arise from lack of sufJicient resources for initiation and execution of multiple instructions concurrently. Control flow problems are caused by branches which force unpredictable changes in the sequential order of code execution. Removing these obstacles allows for the formation of larger basic blocks, resulting in higher ILP. The data flow problems are reduced by increasing the number offunctional units, registers, condition bits, by pipelining the functional units, and using nonblocking caches. The control pow problem is reduced by using techniques such as conditional execution, speculative execution, and software pipelining, leveraging hardware support. Thus, for high ILP, the processor architecture should include a very closely tied hardware and compiler architectures. An architecture that supports the above features, Software Scheduled SuperScalar, is presented in this paper.